The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, three-dimensional (3D) integrated circuits (ICs) have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. A 3D IC may comprise a variety of semiconductor dies stacked together. In particular, the semiconductor dies may be bonded together through a plurality of micro bumps and electrically coupled to each other through a plurality of through vias. For example, active circuits such as logic, memory, processor circuits and the like are fabricated on different wafers and each wafer die is stacked on top of another wafer die using pick-and-place techniques. Through vias are thus used in the stacked dies for connecting dies. In some cases, through vias are often used to connect the integrated circuits on a die to the backside of the die.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.